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general description the max3272/max3272a 2.5gbps limiting amplifiers accept a wide range of input voltages and provide a constant-level output voltage with controlled edge speeds. additional features include power detectors with programmable loss-of-signal (los) indication, an optional squelch function that mutes the data output sig- nal when the input voltage falls below a programmable threshold, and an output polarity selector. these parts exhibit excellent jitter performance and have low power dissipation. the max3272/max3272a feature current-mode logic (cml) data outputs that are tolerant of inductive con- nectors, and are available in a 4mm ? 4mm qfn pack- age or in die form (max3272 only). along with the max3271, the max3272/max3272a are ideal for low- power, compact optical receivers. applications gigabit ethernet optical receivers fibre channel optical receivers system interconnects 2.5gbps optical receivers sonet/sdh receivers features ? single +3.3v power supply ? 33ma supply current ? 5ps deterministic jitter ? 90ps edge speed ? output squelch function ? programmable loss-of-signal function ? cml output interface ? 20-pin 4mm ? 4mm qfn or thin qfn package ? selectable output polarity max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers ________________________________________________________________ maxim integrated products 1 ordering information +3.3v +3.3v +3.3v c az caz1 outpol caz2 v cc 0.1 f 0.1 f th squelch c clos clos 100 ? in- in+ out+ sdi+ sdo+ v cc sdo- sclko- sclko+ sdi- gnd cdr out- max3271 max3272/ max3272a max3873 los gnd loss of signal los r th level t ypical operating circuit 19-2269; rev 3; 11/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet. typical operating circuits continue at end of data sheet. part temp range pin- package package code max3272 egp -40? to +85? 20 qfn g2044-3 max3272e/d -40? to +85? dice* max3272a etp+ -40? to +85? 20 thin qfn t2044-3 max3272aegp -40? to +85? 20 qfn g2044-3 + denotes lead-free package. *dice are designed and guaranteed to operate from -40? to +85?, but are tested only at t a = +25?. evaluation kit available
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers 2 _______________________________________________________________________________________ electrical characteristics (v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. power-supply voltage (v cc ) .................................-0.5v to +6.0v voltage at in+, in- ..........................(v cc - 2.4v) to (v cc + 0.5v) voltage at squelch, caz1, caz2, th, clos ...............................................-0.5v to (v cc + 0.5v) voltage at los, los (max3272)...........................-0.5v to +6.0v voltage at los, los (max3272a) .............-0.5v to (v cc + 0.5v) voltage at level...................................................-0.5v to +2.0v voltage at outpol ...............................................-0.5v to +6.0v current into los, los ..........................................-1ma to +9ma differential input voltage (in+ - in-).................................2.5v p-p continuous current at in+, in- ...........................................50ma continuous current at cml outputs (out+, out-) .........................-25ma to +25ma continuous power dissipation at +85? 20-pin thin qfn (derate 16.9mw/? above +85?) ......1.1w 20-pin qfn (derate 20mw/? above +85?) .................1.3w storage ambient temperature range (t stg ) .................................................-55? to +150? operating junction temperature range (t j ) .....................................................-55? to +150? die attach temperature...................................................+400? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply current i cc (note 2) 33 44 ma input data rate 2.5 gbps input voltage range v in differential 15 1200 mv p-p output deterministic jitter (notes 3, 4, 5) 5 27 ps p-p random jitter (notes 4, 6) 3 ps rms 15mv p-p < v in 30mv p-p 90 130 data output edge speed (20% to 80%) (notes 3, 4) 30mv p-p v in 1200mv p-p 90 115 ps differential input resistance r in in+ to in- 95 100 105 ? ? 2mhz (note 7) 30 db c az = open 0.9 mhz low frequency cutoff f oc c az = 0.1? 1.5 khz output resistance r out single ended to v cc 42.5 50 57.5 ? 2.5ghz 10 single-ended output return loss 2.5ghz to 4.0ghz 9 db differential input return loss 4.0ghz 10 db v il 0.8 outpol input limits v ih 2.4 v los hysteresis (notes 3, 4, 8) 2 3.3 db c clos = open (notes 3, 9, 10) 1 los assert/deassert time c clos = 0.01? (notes 3, 9, 10) 2.3 50 100 ? low los assert level r th = 20k ? (notes 3, 10) 4.5 6.5 mv p-p low los deassert level r th = 20k ? (notes 3, 10) 9.5 12.7 mv p-p medium los assert level r th = 1k ? (notes 3, 10) 7.8 12.9 mv p-p medium los deassert level r th = 1k ? (notes 3, 10) 17.4 22.4 mv p-p high los assert level r th = 80 ? (notes 3, 10) 24.3 48 mv p-p absolute maximum ratings
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v and t a = +25?, unless otherwise noted.) parameter symbol conditions min typ max units high los deassert level r th = 80 ? (notes 3, 10) 73 124.7 mv p-p los output high voltage sinking 30? 2.4 v los output low voltage sourcing 1.2ma 0.4 v squelch input current 400 ? note 1: dice are designed and guaranteed from -40? to +85? but are tested only at t a = +25?. note 2: supply current measurement excludes the current of the cml output stage (16ma typical). see figure 1, power-supply current measurement . note 3: guaranteed by design and characterization. note 4: input edge speed is controlled using 4-pole, lowpass bessel filters with bandwidth approximately 75% of the maximum data rate. note 5: deterministic jitter is measured with a k28.5 pattern (0011 1110 1011 0000 0101). deterministic jitter is the peak-to-peak deviation from ideal time crossings, measured at the zero-level crossings of the differential output per ansi x3.230, annex a. note 6: random jitter is measured with the minimum input signal. for fibre channel and gigabit ethernet applications, the peak- to-peak random jitter is 14.1 times the rms random jitter. note 7: power-supply noise rejection (psnr) is calculated by the equation psnr = 20log ( ? v cc /( ? v out )), where ? v out is the change in differential output voltage due to the power-supply noise, ? v cc . see power-supply noise rejection vs. frequency in the typical operating characteristics . note 8: hysteresis is defined as: 20 ? log(v los-deassert /v los-assert ). note 9: response time to a 10db change in input power. for the specification guaranteed, the power is assumed to switch back and forth between two levels (separated by 10db and equidistant from assert and deassert levels) outside of the two hysteresis thresholds. note 10: all power-detect ac parameters are guaranteed with a 2 23 - 1 prbs, 2.5gbps input, with t he longest possible run of 80cid. t ypical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) 600 650 700 750 800 850 900 950 1000 0102 0304050 output amplitude vs. input amplitude max3272 toc01 v in (mv p-p ) v out (mv p-p ) level = gnd level = open 20 35 30 25 40 45 50 55 60 65 70 -40 10 -15 35 6 085 supply current vs. ambient temperature max3272 toc02 ambient temperature ( c) supply current (ma) 0 6 4 2 8 10 12 14 16 18 20 11 01 00 1000 10,000 deterministic jitter vs. input amplitude max3272 toc03 input amplitude (mv p-p ) deterministic jitter (ps p-p )
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers 4 _______________________________________________________________________________________ t ypical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.) 0 3 2 1 4 5 6 7 8 9 10 11 0 100 1000 10,000 random jitter vs. input amplitude max3272 toc04 input amplitude (mv p-p ) random jitter (ps rms ) c clos = 0.01 f v out v in loss-of-signal with squelch max3272 toc06 20 s/div v los loss of signal treshold vs. r th xxxxxxxx r th ( ? ) los assert (mv) 100k 10k 1k 100 5 10 15 20 25 30 35 40 45 50 0 10 1m data output eye diagram (minimum input) max3272 toc08 2.5gbps 2 23 -1 prbs 15mv p-p input 100ps/div 150mv/ div data output eye diagram (maximum input) max3272 toc09 100ps/div 150mv/ div 2.5gbps 2 23 -1 prbs 1200mv p-p input 0 20 10 40 30 50 60 1k 100k 10k 1m 10m power-supply noise rejection vs. frequency max3272 toc10 frequency (hz) power-supply noise rejection (db) 0 10 5 25 20 15 40 35 30 45 10m 100m 1g 10g input return loss vs. frequency max3272 toc11 frequency (hz) input return loss (db) 2.0 3.0 2.5 4.0 3.5 4.5 5.0 -40 85 los hysteresis vs. ambient temperature max3272 toc05 ambient temperature ( c) hysteresis (db) 10 -15 35 60 r th = 80 ? r th = 20k ? r th = 1k ? 0 10 5 25 20 15 40 35 30 45 10m 100m 1g 10g output return loss vs. frequency max3272 toc12 frequency (hz) output return loss (db)
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers _______________________________________________________________________________________ 5 pin description t ypical operating characteristics (continued) (v cc = +3.3v, t a = +25?, unless otherwise noted.) 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 100k 1m 10m 100m common-mode rejection ratio vs. frequency max3272 toc13 frequency (hz) common-mode rejection ratio (db) pin name function 1, 4, 17 gnd supply ground 2 in+ noninverted input signal 3 in- inverted input signal 5t h loss-of-signal threshold pin. resistor to ground sets the los threshold. 6, 12, 15, 20 v cc power supply 7 clos lo s ti m e- c onstant c ap aci tor c onnecti on. for s on e t ap p l i cati ons, c c l os = 0.01? i s r e com m end ed . 8 squelch squelch input. the squelch function is disabled when squelch is not connected or set to ttl low level. when squelch is set to ttl high level and los is asserted, the data outputs (out+, out-) are forced to static levels. 9 los noninverted loss-of-signal output. los is asserted ttl high when the signal drops below the assert threshold set by the th input. the max3272 does not have esd protection on this pin. the max3272a has esd protection on this pin. 10 los inverted loss-of-signal output. los is asserted ttl low when the signal drops below the assert threshold set by the th input. the max3272 does not have esd protection on this pin. the max3272a has esd protection on this pin. 11 level output current level. when this pin is not connected, the cml output current is approximately 16ma. when this pin is connected to ground, the output current increases to about 20ma. 13 out- inverted data output 14 out+ noninverted data output 16 outpol output polarity control input. connect to gnd for an inversion of polarity through the limiting amplifier and connect to v cc for normal operation. 18 caz2 offset-correction-loop capacitor connection. a capacitor connected between this pin and caz1 extends the time constant of the offset correction loop. typical value of c az is 0.1?. 19 caz1 offset-correction-loop capacitor connection. a capacitor connected between this pin and caz2 extends the time constant of the offset correction loop. typical value of c az is 0.1?. ep exposed pad connect the exposed paddle to board ground for optimal electrical and thermal performance. 0 4 2 8 6 10 12 0 2500 los assert and deassert levels vs. data rate max3272 toc14 data rate (mbps) v in (mv p-p ) 1000 500 1500 2000 2 23 - 1 prbs pattern r th = 20k ? c in = 0.1 f deassert assert
max3272/max3272a detailed description figure 2 is a functional diagram of the max3272/ max3272a, comprising a cml input buffer, power detector and loss-of- signal indicators, gain stage, offset- correction loop, and cml output buffer. cml input buffer the input buffer (figure 3) provides 100 ? input imped- ance between in+ and in-. dc-coupling the inputs is not recommended; this prevents the dc offset-correc- tion circuitry from functioning properly. power detect and loss-of-signal indicator the max3272/max3272a are equipped with loss-of-sig- nal (los) circuitry that indicates when the input signal is below a programmable threshold, set by resistor r th at the th pin (see the typical operating characteristics for appropriate resistor selection). an averaging peak- power detector compares the input signal amplitude with this threshold and feeds the signal-detect informa- tion to the los outputs, which are internally terminated to 8k ? (figure 4). +3.3v, 2.5gbps low-power limiting amplifiers 6 _______________________________________________________________________________________ cml supply current (i cc ) v cc i cc i out 50 ? r th 50 ? control squelch open level open max3272/ max3272a figure 1. power-supply current measurement max3272/ max3272a ttl ttl control power detector in+ in- 100 ? power detector and los indicator cml input buffer cml output buffer offset correction 0.1 f lowpass filter los squelch out+ out- level outpol los caz1 caz2 th clos figure 2. functional diagram
two control voltages v assert , and v deassert , define the los assert and deassert levels. to prevent los chatter in the region of the programmed threshold, approximately 3.3db of hysteresis is built into the los assert/deassert function. once asserted, los is not deasserted until the input amplitude rises to the required level (v deassert ). to facilitate interfacing with +5v modules, the los and los pins on the max3272 do not have internal esd protection. if esd protection is desired, a low-capaci- tance schottky diode or diode array structure, such as the max3202e, is recommended (see the typical operating circuits ). the los and los pins on the max3272a include esd protection and, as a result, cannot be interfaced with +5v modules. gain stage the high-bandwidth gain stage provides approximately 42db of gain. offset-correction loop due to the high gain of the amplifier, the max3272/ max3272a are susceptible to dc offsets in the signal path. in communications systems using nrz data with a 50% duty cycle, pulse-width distortion present in the signal or generated by the transimpedance amplifier appears as input offset and is removed by the offset- cancellation loop. an external capacitor is required between caz1 and caz2 to decouple the offset-can- cellation loop and determine the lower 3db frequency of the signal path. max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers _______________________________________________________________________________________ 7 interface schematics in+ in- 110 ? gnd esd structures v cc 540 ? 540 ? 0.25pf 0.25pf figure 3. input circuit gnd esd structure v cc los 8k ? figure 4a. los output circuit for max3272 gnd esd structure v cc los 8k ? figure 4b. los output circuit for max3272a
cml output buffer the max3272/max3272a cml output circuit (figure 5) provides high tolerance to impedance mismatches and inductive connectors. the output current can be set to two levels using the level pin. when level is uncon- nected, the output current is approximately 16ma. connecting level to ground sets the output current to approximately 20ma. the squelch function is enabled when the squelch pin is set to a ttl high. this func- tion holds out+ and out- to a static level whenever the input signal amplitude drops below the loss-of-sig- nal threshold. this circuit is also equipped with a polari- ty selector, programmed by the outpol pin. when this pin is connected to v cc , no inversion will occur. when connected to ground, the output signal will be inverted. design procedure program the los assert threshold external resistor r th programs the loss-of-signal threshold. see the los threshold vs. r th graph in the the typical operating characteristics section to select the appropriate resistor. select the coupling capacitors when ac-coupling, input and output coupling capaci- tors (c in and c out ) should be selected to minimize the receiver? deterministic jitter. jitter is decreased as the input low-frequency cutoff (f in ) is decreased: f in = 1 / [2 (50)(c in )] for atm/sonet or other applications using scrambled nrz data, select (c in , c out ) 0.1?, which provides f in < 32khz. for fibre channel, gigabit ethernet, or other applications using 8b/10b data coding, select (c in , c out ) 0.01?, which provides f in < 320khz. refer to application note hfan-1.1: choosing ac- coupling capacitors . select the offset-correction capacitor the capacitor between caz1 and caz2 determines the time constant of the signal path dc offset-cancellation loop. to maintain stability, it is important to keep a one- decade separation between f in and the low-frequency cutoff (f oc ) associated with the dc offset-cancellation circuit. for atm/sonet or other applications using scrambled nrz data, f in < 32khz, so f ocmax < 3.2khz. therefore, c az = 0.1? (f oc = 2khz). for fibre channel or gigabit ethernet applications, leave pins caz1 and caz2 open. program the los time constant external capacitor c clos programs the los assert and deassert times. when inputting data with many consecutive identical digits (cids), a longer time con- stant may be advantageous, so los does not flag incorrectly. in this case, connect the clos pin to a 0.01? capacitor to set the assert time in the range of 2? to 100?. for scrambled data where the mark den- sity is kept at 50%, a shorter time constant may be desirable. leave the clos pin open for a shorter time constant of about 1?. max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers 8 _______________________________________________________________________________________ gnd level esd structures v cc 50 ? 50 ? out- out+ figure 5. cml output circuit
applications information optical hysteresis in an optical receiver, the electrical power change at the limiting amplifier is 2 times the optical power change. as an example, if a receiver? optical input power (x) increases by a factor of two, and the preamplifier is lin- ear, then the voltage input to the limiting amplifier also increases by a factor of two. the optical power change is 10log(2x / x) = 10log(2) = +3db. at the limiting amplifier, the electrical power change is: the max3272 typical voltage hysteresis is 3.3db. this provides an optical hysteresis of 1.65db. 10log 2v / r v/ r 10log(2 ) 20log(2) 6db in 2 in in 2 in 2 () ===+ max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers _______________________________________________________________________________________ 9 1 2 3 4 5 15 14 13 12 11 20 19 18 17 16 678910 gnd in+ in- gnd note: exposed pad must be connected to supply ground. th v cc out+ out- v cc level v cc caz1 caz2 gnd outpol v cc clos squelch los los top view qfn* max3272/ max3272a 1 2 3 4 5 15 14 13 12 11 20 19 18 17 16 678910 gnd in+ in- gnd note: exposed pad must be connected to supply ground. th v cc out+ out- v cc level v cc caz1 caz2 gnd outpol v cc clos squelch los los thin qfn* max3272a + pin configuration pad coordinates pad name coordinates (m) 1 gnd 47, 836 2 in+ 47, 603 3 in- 47, 425 4 gnd 47, 237 5t h 47, 47 6v cc 255, -154 7 clos 436, -154 8 squelch 645, -154 9 los 850, -154 10 los 1063, -154 11 level 1331, 37 12 v cc 1331, 212 13 out- 1331, 421 14 out+ 1331, 573 15 v cc 1331, 780 16 outpol 1119, 1042 17 gnd 957, 1042 18 caz2 773, 1042 19 caz1 583, 1042 20 n.c. 422, 1042 21 v cc 268, 1042 coordinates are for the center of the pad. coordinate 0, 0 is the lower left corner of the passivation open- ing for pad 5.
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers 10 ______________________________________________________________________________________ +3.3v +3.3v +3.3v c az caz1 outpol caz2 v cc 0.1 f 0.1 f th squelch c clos *the max3202e provides esd protection on the los pin clos 100 ? in- in+ out+ sdi+ sdo+ v cc sdo- sclko- sclko+ sdi- gnd cdr out- max3271 max3272 max3873 los gnd loss of signal los r th level +3.3v v cc i/01 gnd max3202e* t ypical operating circuit (continued) wire bonding die for high-current density and reliable operation, the max3272 uses gold metallization. make connections to the dice with gold wire only, and use ball-bonding tech- niques (wedge bonding is not recommended). die pad dimensions are 94.4 microns by 94.4 microns. die thickness is 15 mils (0.375mm).
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers ______________________________________________________________________________________ 11 chip information v cc (pad 21) n.c. (pad 20) caz1 (pad 19) caz2 (pad 18) gnd (pad 17) outpol (pad 16) v cc (pad 6) clos (pad 7) squelch (pad 8) los (pad 9) los (pad 10) v cc (pad 15) out+ (pad 14) out- (pad 13) v cc (pad 12) level (pad 11) gnd (pad 1) in+ (pad 2) in- (pad 3) gnd (pad 4) th (pad 5) 62 mils 1.57mm 66 mils 1.68mm transistor count: 726 process: sige bipolar substrate: insulator, connect to gnd die size: 1.68mm ? 1.57mm die thickness: 15 mils
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers 12 ______________________________________________________________________________________ 12,16,20, 24l qfn.eps e 1 2 21-0106 package outline 12,16,20,24l qfn, 4x4x0.90 mm p ack ag e information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers ______________________________________________________________________________________ 13 e 2 2 21-0106 package outline 12,16,20,24l qfn, 4x4x0.90 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max3272/max3272a +3.3v, 2.5gbps low-power limiting amplifiers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 24l qfn thin.eps c 1 2 21-0139 package outline 12, 16, 20, 24l thin qfn, 4x4x0.8mm c 2 2 21-0139 package outline 12, 16, 20, 24l thin qfn, 4x4x0.8mm

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